Datasheet

Table Of Contents

35.6.4 DMA, Interrupts, and Events

Table 35-4. Module Request for SERCOM SPI

Condition Request

DMA Interrupt Event

Data Register Empty (DRE) Yes

(request cleared when data is written)

Yes NA

Receive Complete (RXC) Yes

(request cleared when data is read)

Yes

Transmit Complete (TXC) NA Yes

Slave Select low (SSL) NA Yes

Error (ERROR) NA Yes

35.6.4.1 DMA Operation

The SPI generates the following DMA requests:

• Data received (RX): The request is set when data is available in the receive FIFO. The request is

cleared when DATA is read.

• Data transmit (TX): The request is set when the transmit buffer (TX DATA) is empty. The request is

cleared when DATA is written.

35.6.4.2 Interrupts

The SPI has the following interrupt sources. These are asynchronous interrupts, and can wake-up the

device from any Sleep mode:

• Data Register Empty (DRE)

• Receive Complete (RXC)

• Transmit Complete (TXC)

• Slave Select Low (SSL)

• Error (ERROR)

Each interrupt source has its own Interrupt flag. The Interrupt flag in the Interrupt Flag Status and Clear

enabled by writing '1' to the corresponding bit in the Interrupt Enable Set register (INTENSET), and

disabled by writing '1' to the corresponding bit in the Interrupt Enable Clear register (INTENCLR).

An interrupt request is generated when the Interrupt flag is set and if the corresponding interrupt is

enabled. The interrupt request remains active until either the Interrupt flag is cleared, the interrupt is

disabled, or the SPI is reset. For details on clearing Interrupt flags, refer to the INTFLAG register

description.

The value of INTFLAG indicates which interrupt is executed. Note that interrupts must be globally

enabled for interrupt requests. Refer to Nested Vector Interrupt Controller for details.