Datasheet

35.6.2 Basic Operation
35.6.2.1 Initialization
The following registers are enable-protected, meaning that they can only be written when the SPI is
disabled (CTRL.ENABLE=0):
• Control A register (CTRLA), except Enable (CTRLA.ENABLE) and Software Reset (CTRLA.SWRST)
• Control B register (CTRLB), except Receiver Enable (CTRLB.RXEN)
• Baud register (BAUD)
• Address register (ADDR)
When the SPI is enabled or is being enabled (CTRLA.ENABLE=1), any writing to these registers will be
discarded.
When the SPI is being disabled, writing to these registers will be completed after the disabling.
Enable-protection is denoted by the Enable-Protection property in the register description.
Initialize the SPI by following these steps:
1. Select SPI mode in master/slave operation in the Operating Mode bit group in the CTRLA register
(CTRLA.MODE= 0x2 or 0x3 ).
2. Select Transfer mode for the Clock Polarity bit and the Clock Phase bit in the CTRLA register
(CTRLA.CPOL and CTRLA.CPHA) if desired.
3. Select the Frame Format value in the CTRLA register (CTRLA.FORM).
4. Configure the Data In Pinout field in the Control A register (CTRLA.DIPO) for SERCOM pads of the
receiver.
5. Configure the Data Out Pinout bit group in the Control A register (CTRLA.DOPO) for SERCOM
pads of the transmitter.
6. Select the Character Size value in the CTRLB register (CTRLB.CHSIZE).
7. Write the Data Order bit in the CTRLA register (CTRLA.DORD) for data direction.
8. If the SPI is used in Master mode:
8.1. Select the desired baud rate by writing to the Baud register (BAUD).
8.2. If Hardware SS control is required, write '1' to the Master Slave Select Enable bit in CTRLB
register (CTRLB.MSSEN).
9. Enable the receiver by writing the Receiver Enable bit in the CTRLB register (CTRLB.RXEN=1).
35.6.2.2 Enabling, Disabling, and Resetting
This peripheral is enabled by writing '1' to the Enable bit in the Control A register (CTRLA.ENABLE), and
disabled by writing '0' to it.
Writing ‘1’ to the Software Reset bit in the Control A register (CTRLA.SWRST) will reset all registers of
this peripheral to their initial states, except the DBGCTRL register, and the peripheral is disabled.
Refer to the CTRLA register description for details.
35.6.2.3 Clock Generation
In the SPI master operation (CTRLA.MODE=0x3), the serial clock (SCK) is generated internally by the
SERCOM Baud Rate Generator (BRG).
In SPI mode, the BRG is set to Synchronous mode. The 8-bit Baud register (BAUD) value is used for
generating SCK and clocking the Shift register. Refer to Clock Generation – Baud-Rate Generator for
more details.
SAM D5x/E5x Family Data Sheet
SERCOM SPI – SERCOM Serial Peripheral Interface
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 973