Datasheet

35.5.8 Register Access Protection
Registers with write access can be write-protected optionally by the Peripheral Access Controller (PAC).
PAC write protection is not available for the following registers:
• Interrupt Flag Clear and Status register (INTFLAG)
• Status register (STATUS)
• Data register (DATA)
Optional PAC write protection is denoted by the "PAC Write-Protection" property in each individual
register description.
Write-protection does not apply to accesses through an external debugger.
Related Links
27. PAC - Peripheral Access Controller
35.5.9 Analog Connections
Not applicable.
35.6 Functional Description
35.6.1 Principle of Operation
The SPI is a high-speed synchronous data transfer interface. It allows high-speed communication
between the device and peripheral devices.
The SPI can operate as master or slave. As master, the SPI initiates and controls all data transactions.
The SPI is single buffered for transmitting and double buffered for receiving.
When transmitting data, the Data register can be loaded with the next character to be transmitted during
the current transmission.
When receiving, the data is transferred to the two-level receive buffer, and the receiver is ready for a new
character.
The SPI transaction format is shown in SPI Transaction Format. Each transaction can contain one or
more characters. The character size is configurable, and can be either 8 or 9 bits.
Figure 35-2. SPI Transaction Format
Character
Transaction
MOSI/MISO
_SS
Character 0 Character 1 Character 2
The SPI master must pull the slave select line (SS) of the desired slave low to initiate a transaction. The
master and slave prepare data to send via their respective Shift registers, and the master generates the
serial clock on the SCK line.
Data are always shifted from master to slave on the Master Output Slave Input line (MOSI); data is shifted
from slave to master on the Master Input Slave Output line (MISO).
Each time character is shifted out from the master, a character will be shifted out from the slave
simultaneously. To signal the end of a transaction, the master will pull the SS line high
SAM D5x/E5x Family Data Sheet
SERCOM SPI – SERCOM Serial Peripheral Interface
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 972