Datasheet

34.8.7 Interrupt Enable Set
Name: INTENSET
Offset: 0x16
Reset: 0x00
Property: PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes
in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Bit 7 6 5 4 3 2 1 0
ERROR RXBRK CTSIC RXS RXC TXC DRE
Access
R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
Bit 7 – ERROR Error Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the Error Interrupt Enable bit, which enables the Error interrupt.
Value Description
0
Error interrupt is disabled.
1
Error interrupt is enabled.
Bit 5 – RXBRK Receive Break Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the Receive Break Interrupt Enable bit, which enables the Receive Break
interrupt.
Value Description
0
Receive Break interrupt is disabled.
1
Receive Break interrupt is enabled.
Bit 4 – CTSIC Clear to Send Input Change Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the Clear To Send Input Change Interrupt Enable bit, which enables the Clear
To Send Input Change interrupt.
Value Description
0
Clear To Send Input Change interrupt is disabled.
1
Clear To Send Input Change interrupt is enabled.
Bit 3 – RXS Receive Start Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the Receive Start Interrupt Enable bit, which enables the Receive Start
interrupt.
Value Description
0
Receive Start interrupt is disabled.
1
Receive Start interrupt is enabled.
Bit 2 – RXC Receive Complete Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the Receive Complete Interrupt Enable bit, which enables the Receive
Complete interrupt.
SAM D5x/E5x Family Data Sheet
SERCOM USART - SERCOM Synchronous and Asyn...
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 957