Datasheet

34.8.3 Control C
Name: CTRLC
Offset: 0x08
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected
Bit 31 30 29 28 27 26 25 24
DATA32B[1:0]
Access
R/W R/W
Reset 0 0
Bit 23 22 21 20 19 18 17 16
MAXITER[2:0] DSNACK INACK
Access
R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
HDRDLY[1:0] BRKLEN[1:0]
Access
R/W R/W R/W R/W
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
GTIME[2:0]
Access
R/W R/W R/W
Reset 0 0 0
Bits 25:24 – DATA32B[1:0] Data 32 Bit
These bits configure 32-bit Extension for read and write transactions to the DATA register.
When disabled, access is according to CTRLB.CHSIZE.
Value Description
0x0
DATA reads (for received data) and writes (for transmit data) according to CTRLB.CHSIZE.
0x1
DATA reads according to CTRLB.CHSIZE.
DATA writes using 32-bit Extension.
0x2
DATA reads using 32-bit Extension.
DATA writes according to CTRLB.CHSIZE.
0x3
DATA reads and writes using 32-bit Extension.
Bits 22:20 – MAXITER[2:0] Maximum Iterations
These bits define the maximum number of retransmit iterations.
These bits also define the successive NACKs sent to the remote transmitter when CTRLC.DSNACK is
set.
This field is only valid when using ISO7816 T=0 mode (CTRLA.MODE=0x7 and CTRLA.CMODE=0).
Bit 17 – DSNACK Disable Successive Not Acknowledge
This bit controls how many times NACK will be sent on parity error reception.
This bit is only valid in ISO7816 T=0 mode and when CTRLC.INACK=0.
SAM D5x/E5x Family Data Sheet
SERCOM USART - SERCOM Synchronous and Asyn...
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 951