Datasheet

34.8.2 Control B
Name: CTRLB
Offset: 0x04
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected, Write-Synchronized
Bit 31 30 29 28 27 26 25 24
LINCMD[1:0]
Access
R/W R/W
Reset 0 0
Bit 23 22 21 20 19 18 17 16
RXEN TXEN
Access
R/W R/W
Reset 0 0
Bit 15 14 13 12 11 10 9 8
PMODE ENC SFDE COLDEN
Access
R/W R/W R/W R/W
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
SBMODE CHSIZE[2:0]
Access
R/W R/W R/W R/W
Reset 0 0 0 0
Bits 25:24 – LINCMD[1:0] LIN Command
These bits define the LIN header transmission control. This field is only valid in LIN master mode
(CTRLA.FORM= LIN Master).
These are strobe bits and will always read back as zero.
These bits are not enable-protected.
Value Description
0x0
Normal USART transmission.
0x1
Break field is transmitted when DATA is written.
0x2
Break, sync and identifier are automatically transmitted when DATA is written with the
identifier.
0x3
Reserved
Bit 17 – RXEN Receiver Enable
Writing '0' to this bit will disable the USART receiver. Disabling the receiver will flush the receive buffer
and clear the FERR, PERR and BUFOVF bits in the STATUS register.
Writing '1' to CTRLB.RXEN when the USART is disabled will set CTRLB.RXEN immediately. When the
USART is enabled, CTRLB.RXEN will be cleared, and SYNCBUSY.CTRLB will be set and remain set
until the receiver is enabled. When the receiver is enabled, CTRLB.RXEN will read back as '1'.
Writing '1' to CTRLB.RXEN when the USART is enabled will set SYNCBUSY.CTRLB, which will remain
set until the receiver is enabled, and CTRLB.RXEN will read back as '1'.
This bit is not enable-protected.
SAM D5x/E5x Family Data Sheet
SERCOM USART - SERCOM Synchronous and Asyn...
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 948