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10.2 Nested Vector Interrupt Controller
34.6.4.3 Events
Not applicable.
34.6.5 Sleep Mode Operation
The behavior in Sleep mode is depending on the clock source and the Run In Standby bit in the Control A
register (CTRLA.RUNSTDBY):
• Internal clocking, CTRLA.RUNSTDBY=1: GCLK_SERCOMx_CORE can be enabled in all Sleep
modes. Any interrupt can wake-up the device.
• External clocking, CTRLA.RUNSTDBY=1: The Receive Complete interrupt(s) can wake-up the
device.
• Internal clocking, CTRLA.RUNSTDBY=0: Internal clock will be disabled, after any ongoing transfer
was completed. The Receive Complete interrupt(s) can wake-up the device.
• External clocking, CTRLA.RUNSTDBY=0: External clock will be disconnected, after any ongoing
transfer was completed. All reception will be dropped.
34.6.6 Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers
need to be synchronized when written or read.
The following bits are synchronized when written:
• Software Reset bit in the CTRLA register (CTRLA.SWRST)
• Enable bit in the CTRLA register (CTRLA.ENABLE)
• Receiver Enable bit in the CTRLB register (CTRLB.RXEN)
• Transmitter Enable bit in the Control B register (CTRLB.TXEN)
Note: CTRLB.RXEN is write-synchronized somewhat differently. See also 34.8.2 CTRLB for details.
Required write synchronization is denoted by the "Write-Synchronized" property in the register
description.
SAM D5x/E5x Family Data Sheet
SERCOM USART - SERCOM Synchronous and Asyn...
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Datasheet
DS60001507E-page 941