Datasheet

The figure below shows the order of transmit and receive when using 32-bit extension. Bytes are
transmitted or received, and stored in order from 0 to 3. Only 8-bit and smaller character sizes are
supported. If the character size is less than 8 bits, characters will still be 8-bit aligned within the 32-bit
APB write or read. The unused bits within each byte will be zero for received data and unused for
transmit data.
Figure 34-22. 32-bit Extension Ordering
BYTE0
BYTE1
BYTE2
BYTE3
APB Write/Read
31
0
Bit Position
A receive transaction using 32-bit extension is in the next figure. The Receive Complete flag
(INTFLAG.RXC) is raised every four received Bytes. For transmit transactions, the Data Register Empty
flag (INTFLAG.DRE) is raised instead of INTFLAG.RXC.
Figure 34-23. 32-bit Extension Receive Operation
Byte 0
S
W
RXC interrupt
Byte 1
Byte 2
Byte 3
Data Length Configuration
When the Data Length Enable bit field in the Length register (LENGTH.LENEN) is written to 0x1 or 0x2,
the Data Length bit (LENGTH.LEN) determines the number of characters to be transmitted or received
from 1 to 255.
Note: There is one internal length counter that can be used for either transmit (LENGTH.LENEN=0x1)
or receive (LENGTH.LENEN=0x2), but not for both simultaneously.
The LENGTH register must be written before the frame begins. If LENGTH.LEN is not a multiple of 4
Bytes, the final INTFLAG.RXC/DRE interrupt will be raised when the last byte is received/sent. The
internal length counter is reset when LENGTH.LEN is reached or when LENGTH.LENEN is written to
0x0.
Writing the LENGTH register while a frame is in progress will produce unpredictable results. If
LENGTH.LENEN is not set and a frame is not a multiple of 4 Bytes, the remainder may be lost.
Attempting to use the length counter for transmit and receive at the same time will produce unpredictable
results.
SAM D5x/E5x Family Data Sheet
SERCOM USART - SERCOM Synchronous and Asyn...
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 939