Datasheet

1. Abort the current transfer.
2. Flush the transmit buffer.
3. Disable transmitter (CTRLB.TXEN=0)
– This is done after a synchronization delay. The CTRLB Synchronization Busy bit
(SYNCBUSY.CTRLB) will be set until this is complete.
– After disabling, the TxD pin will be tri-stated.
4. Set the Collision Detected bit (STATUS.COLL) along with the Error Interrupt Flag
(INTFLAG.ERROR).
5. Set the Transmit Complete Interrupt Flag (INTFLAG.TXC), since the transmit buffer no longer
contains data.
After a collision, software must manually enable the transmitter again before continuing, after assuring
that the CTRLB Synchronization Busy bit (SYNCBUSY.CTRLB) is not set.
34.6.3.9 Loop-Back Mode
For Loop-Back mode, configure the Receive Data Pinout (CTRLA.RXPO) and Transmit Data Pinout
(CTRLA.TXPO) to use the same data pins for transmit and receive. The loop-back is through the pad, so
the signal is also available externally.
34.6.3.10 Start-of-Frame Detection
The USART start-of-frame detector can wake-up the CPU when it detects a Start bit. In Standby Sleep
mode, the internal fast start-up oscillator must be selected as the GCLK_SERCOMx_CORE source.
When a 1-to-0 transition is detected on RxD, the 8 MHz Internal Oscillator is powered up and the USART
clock is enabled. After start-up, the rest of the data frame can be received, provided that the baud rate is
slow enough in relation to the fast start-up internal oscillator start-up time. Refer to the Electrical
Characteristics chapters for details. The start-up time of this oscillator varies with supply voltage and
temperature.
The USART start-of-frame detection works both in Asynchronous and Synchronous modes. It is enabled
by writing ‘1’ to the Start of Frame Detection Enable bit in the Control B register (CTRLB.SFDE).
If the Receive Start Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.RXS) is set, the
Receive Start interrupt is generated immediately when a start is detected.
When using start-of-frame detection without the Receive Start interrupt, start detection will force the 8
MHz internal oscillator and USART clock active while the frame is being received. In this case, the CPU
will not wake up until the receive complete interrupt is generated.
34.6.3.11 Sample Adjustment
In Asynchronous mode (CTRLA.CMODE=0), three samples in the middle are used to determine the value
based on majority voting. The three samples used for voting can be selected using the Sample
Adjustment bit field in Control A register (CTRLA.SAMPA). When CTRLA.SAMPA=0, samples 7-8-9 are
used for 16x oversampling, and samples 3-4-5 are used for 8x oversampling.
34.6.3.12 32-bit Extension
For better system bus utilization, 32-bit data receive and transmit can be enabled separately by writing to
the Data 32-bit bit field in the Control C register (CTRLC.DATA32B). When enabled, writes and/or reads
to the DATA register are 32 bit in size.
If frames are not multiples of 4 Bytes, the length counter (LENGTH.LEN) and length enable
(LENGTH.LENEN) must be configured before data transfer begins, LENGTH.LEN must be enabled only
when CTRLC.DATA32B is enabled.
SAM D5x/E5x Family Data Sheet
SERCOM USART - SERCOM Synchronous and Asyn...
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 938