Datasheet

is the same for internal and external clocks. Data input on the RxD pin is sampled at the opposite XCK
clock edge when data is driven on the TxD pin.
The Clock Polarity bit in the Control A register (CTRLA.CPOL) selects which XCK clock edge is used for
RxD sampling, and which is used for TxD change:
When CTRLA.CPOL is '0', the data will be changed on the rising edge of XCK, and sampled on the falling
edge of XCK.
When CTRLA.CPOL is '1', the data will be changed on the falling edge of XCK, and sampled on the rising
edge of XCK.
Figure 34-4. Synchronous Mode XCK Timing
XCK
RxD / TxD
CTRLA.CPOL=1
Change
Sample
XCK
RxD / TxD
CTRLA.CPOL=0
Change
Sample
When the clock is provided through XCK (CTRLA.MODE=0x0), the Shift registers operate directly on the
XCK clock. This means that XCK is not synchronized with the system clock and, therefore, can operate at
frequencies up to the system frequency.
34.6.2.4 Data Register
The USART Transmit Data register (TxDATA) and USART Receive Data register (RxDATA) share the
same I/O address, referred to as the Data register (DATA). Writing the DATA register will update the
TxDATA register. Reading the DATA register will return the contents of the RxDATA register.
34.6.2.5 Data Transmission
Data transmission is initiated by writing the data to be sent into the DATA register. Then, the data in
TxDATA will be moved to the Shift register when the Shift register is empty and ready to send a new
frame. After the Shift register is loaded with data, the data frame will be transmitted.
When the entire data frame including Stop bit(s) has been transmitted and no new data was written to
DATA, the Transmit Complete Interrupt flag in the Interrupt Flag Status and Clear register
(INTFLAG.TXC) will be set, and the optional interrupt will be generated.
The Data Register Empty flag in the Interrupt Flag Status and Clear register (INTFLAG.DRE) indicates
that the register is empty and ready for new data. The DATA register should only be written to when
INTFLAG.DRE is set.
34.6.2.5.1 Disabling the Transmitter
The transmitter is disabled by writing '0' to the Transmitter Enable bit in the CTRLB register
(CTRLB.TXEN).
Disabling the transmitter will complete only after any ongoing and pending transmissions are completed,
i.e., there is no data in the Transmit Shift register and TxDATA to transmit.
SAM D5x/E5x Family Data Sheet
SERCOM USART - SERCOM Synchronous and Asyn...
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Datasheet
DS60001507E-page 928