Datasheet

7.2. Configure the Parity Mode bit in the CTRLB register (CTRLB.PMODE) for even or odd
parity.
8. Configure the number of stop bits in the Stop Bit Mode bit in the CTRLB register
(CTRLB.SBMODE).
9. When using an internal clock, write the Baud register (BAUD) to generate the desired baud rate.
10. Enable the transmitter and receiver by writing '1' to the Receiver Enable and Transmitter Enable
bits in the CTRLB register (CTRLB.RXEN and CTRLB.TXEN).
34.6.2.2 Enabling, Disabling, and Resetting
This peripheral is enabled by writing '1' to the Enable bit in the Control A register (CTRLA.ENABLE), and
disabled by writing '0' to it.
Writing ‘1’ to the Software Reset bit in the Control A register (CTRLA.SWRST) will reset all registers of
this peripheral to their initial states, except the DBGCTRL register, and the peripheral is disabled.
Refer to the CTRLA register description for details.
34.6.2.3 Clock Generation and Selection
For both Synchronous and Asynchronous modes, the clock used for shifting and sampling data can be
generated internally by the SERCOM baud-rate generator or supplied externally through the XCK line.
The Synchronous mode is selected by writing a '1' to the Communication Mode bit in the Control A
register (CTRLA.CMODE), the Asynchronous mode is selected by writing a zero to CTRLA.CMODE.
The internal clock source is selected by writing 0x1 to the Operation Mode bit field in the Control A
register (CTRLA.MODE), the external clock source is selected by writing 0x0 to CTRLA.MODE.
The SERCOM baud-rate generator is configured as in the figure below.
In Asynchronous mode (CTRLA.CMODE=0), the 16-bit Baud register value is used.
In Synchronous mode (CTRLA.CMODE=1), the eight LSBs of the Baud register are used. Refer to Clock
Generation – Baud-Rate Generator for details on configuring the baud rate.
Figure 34-3. Clock Generation
XCK
CTRLA.MODE[0]
1
0
XCKInternal Clk
(GCLK)
Baud Rate Generator
Base
Period
/2
/8
/2 /8/1
1
0
1
0
0
1
Tx Clk
Rx Clk
CTRLA.CMODE
Related Links
33.6.2.3 Clock Generation – Baud-Rate Generator
33.6.2.3.1 Asynchronous Arithmetic Mode BAUD Value Selection
34.6.2.3.1 Synchronous Clock Operation
In Synchronous mode, the CTRLA.MODE bit field determines whether the transmission clock line (XCK)
serves either as input or output. The dependency between clock edges, data sampling, and data change
SAM D5x/E5x Family Data Sheet
SERCOM USART - SERCOM Synchronous and Asyn...
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Datasheet
DS60001507E-page 927