Datasheet

10.2 Nested Vector Interrupt Controller
34.5.6 Events
Not applicable.
34.5.7 Debug Operation
When the CPU is halted in Debug mode, this peripheral will continue normal operation. If the peripheral is
configured to require periodical service by the CPU through interrupts or similar, improper operation or
data loss may result during debugging. This peripheral can be forced to halt operation during debugging -
refer to the Debug Control (DBGCTRL) register for details.
Related Links
34.8.14 DBGCTRL
34.5.8 Register Access Protection
Registers with write access can be write-protected optionally by the Peripheral Access Controller (PAC).
PAC write protection is not available for the following registers:
• Interrupt Flag Clear and Status register (INTFLAG)
• Status register (STATUS)
• Data register (DATA)
Optional PAC write protection is denoted by the "PAC Write-Protection" property in each individual
register description.
Write-protection does not apply to accesses through an external debugger.
Related Links
27. PAC - Peripheral Access Controller
34.5.9 Analog Connections
Not applicable.
34.6 Functional Description
34.6.1 Principle of Operation
The USART uses the following lines for data transfer:
• RxD for receiving
• TxD for transmitting
• XCK for the transmission clock in synchronous operation
USART data transfer is frame based. A serial frame consists of:
• 1 start bit
• From 5 to 9 data bits (MSB or LSB first)
• No, even or odd parity bit
• 1 or 2 stop bits
A frame starts with the Start bit followed by one character of Data bits. If enabled, the parity bit is inserted
after the Data bits and before the first Stop bit. After the stop bit(s) of a frame, either the next frame can
SAM D5x/E5x Family Data Sheet
SERCOM USART - SERCOM Synchronous and Asyn...
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Datasheet
DS60001507E-page 925