Datasheet

Table 34-2. USART Pin Configuration
Pin Pin Configuration
TxD Output
RxD Input
XCK Output or input
The combined configuration of PORT and the Transmit Data Pinout and Receive Data Pinout bit fields in
the Control A register (CTRLA.TXPO and CTRLA.RXPO, respectively) will define the physical position of
the USART signals in Table 34-2.
Related Links
32. PORT - I/O Pin Controller
34.5.2 Power Management
This peripheral can continue to operate in any Sleep mode where its source clock is running. The
interrupts can wake-up the device from Sleep modes.
Related Links
18. PM – Power Manager
34.5.3 Clocks
The SERCOM bus clock (CLK_SERCOMx_APB) can be enabled and disabled in the Main Clock
Controller. Refer to Peripheral Clock Masking for details and default status of this clock.
A generic clock (GCLK_SERCOMx_CORE) is required to clock the SERCOMx_CORE. This clock must
be configured and enabled in the Generic Clock Controller before using the SERCOMx_CORE. Refer to
GCLK - Generic Clock Controller for details.
This generic clock is asynchronous to the bus clock (CLK_SERCOMx_APB). Therefore, writing to certain
registers will require synchronization to the clock domains. Refer to Synchronization for further details.
Related Links
15.6.2.6 Peripheral Clock Masking
34.6.6 Synchronization
14. GCLK - Generic Clock Controller
34.5.4 DMA
The DMA request lines are connected to the DMA Controller (DMAC). In order to use DMA requests with
this peripheral the DMAC must be configured first. Refer to DMAC – Direct Memory Access Controller for
details.
Related Links
22. DMAC – Direct Memory Access Controller
34.5.5 Interrupts
The interrupt request line is connected to the Interrupt Controller. In order to use interrupt requests of this
peripheral, the Interrupt Controller (NVIC) must be configured first. Refer to Nested Vector Interrupt
Controller for details.
Related Links
SAM D5x/E5x Family Data Sheet
SERCOM USART - SERCOM Synchronous and Asyn...
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Datasheet
DS60001507E-page 924