Datasheet

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Figure 33-5. Two Unique Addresses

ADDRMASK

rx shift register

ADDR

Match

33.6.3.1.3 Address Range

The range of addresses between and including ADDR.ADDR and ADDR.ADDRMASK will cause a match.

ADDR.ADDR and ADDR.ADDRMASK can be set to any two addresses, with ADDR.ADDR acting as the

upper limit and ADDR.ADDRMASK acting as the lower limit.

Figure 33-6. Address Range

ADDRMASK rx shift register ADDR

Match

33.6.4 DMA Operation

The available DMA interrupts and their depend on the operation mode of the SERCOM peripheral. Refer

to the Functional Description sections of the respective SERCOM mode.

Related Links

34. SERCOM USART - SERCOM Synchronous and Asynchronous Receiver and Transmitter

35. SERCOM SPI – SERCOM Serial Peripheral Interface

36. SERCOM I2C – Inter-Integrated Circuit

33.6.5 Interrupts

Interrupt sources are mode specific. See the respective SERCOM mode chapters for details.

Each interrupt source has its own Interrupt flag.

The Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG) will be set when the Interrupt

condition is met.

Each interrupt can be individually enabled by writing '1' to the corresponding bit in the Interrupt Enable

Set register (INTENSET), and disabled by writing '1' to the corresponding bit in the Interrupt Enable Clear

An interrupt request is generated when the Interrupt flag is set and the corresponding interrupt is enabled.

The interrupt request remains active until either the Interrupt flag is cleared, the interrupt is disabled, or

the SERCOM is reset. For details on clearing Interrupt flags, refer to the INTFLAG register description.

The value of INTFLAG indicates which Interrupt condition occurred. The user must read the INTFLAG

Note: Interrupts must be globally enabled for interrupt requests.