Datasheet

33.3 Block Diagram
Figure 33-1. SERCOM Block Diagram
TX/RX DATA
CONTROL/STATUS
Mode n
SERCOM
BAUD/ADDR
Transmitter
Register Interface
Serial Engine
Receiver
Mode 0
Mode 1
Baud Rate
Generator
Address
Match
Mode Specific
PAD[3:0]
33.4 Signal Description
See the respective SERCOM mode chapters for details.
Related Links
34. SERCOM USART - SERCOM Synchronous and Asynchronous Receiver and Transmitter
35. SERCOM SPI – SERCOM Serial Peripheral Interface
36. SERCOM I2C – Inter-Integrated Circuit
33.5 Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
33.5.1 I/O Lines
Using the SERCOM I/O lines requires the I/O pins to be configured using port configuration (PORT).
The SERCOM has four internal pads, PAD[3:0], and the signals from I
2
C, SPI and USART are routed
through these SERCOM pads through a multiplexer. The configuration of the multiplexer is available from
the different SERCOM modes. Refer to the mode specific chapters for additional information.
Related Links
34. SERCOM USART - SERCOM Synchronous and Asynchronous Receiver and Transmitter
35. SERCOM SPI – SERCOM Serial Peripheral Interface
36. SERCOM I2C – Inter-Integrated Circuit
32. PORT - I/O Pin Controller
34.3 Block Diagram
33.5.2 Power Management
The SERCOM can operate in any Sleep mode provided the selected clock source is running. SERCOM
interrupts can be configured to wake the device from sleep modes.
SAM D5x/E5x Family Data Sheet
SERCOM – Serial Communication Interface
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 914