Datasheet

Bits 6:5 – WAYNUM[1:0] Number of Way
This bit field configures the mapping of the cache.
Value Name Description
0x0
DMAPPED Direct Mapped Cache
0x1
ARCH2WAY 2-WAY set associative
0x2
ARCH4WAY 4-WAY set associative
0x3
ARCH8WAY 8-WAY set associative
Bit 4 – RRP Round Robin Policy Supported
Writing a '0' to this bit disables Round Robin Policy.
Writing a '1' to this bit enables Round Robin Policy.
Value Description
0
Round Robin Policy is disabled.
1
Round Robin Policy is enabled.
Bit 3 – LRUP Least Recently Used Policy Supported
Writing a '0' to this bit disables the Least Recently Used Policy Supported.
Writing a '1' to this bit enables the Least Recently Used Policy Supported.
Bit 2 – RANDP Random Selection Policy Supported
Writing a '0' to this bit disables the Random Selection Policy Supported.
Writing a '1' to this bit enables the Random Selection Policy Supported.
Bit 1 – GCLK Dynamic Clock Gating
Writing a '0' to this bit disables the Dynamic Clock Gating feature.
Writing a '1' to this bit enables the Dynamic Clock Gating feature.
Value Description
0
Dynamic Clock Gating is disabled.
1
Dynamic Clock Gating is enabled.
Bit 0 – AP Access Port Access Allowed
Writing a '0' to this bit disables the Access Port Access Allowed.
Writing a '1' to this bit enables the Access Port Access Allowed.
SAM D5x/E5x Family Data Sheet
CMCC - Cortex M Cache Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 91