Datasheet

32.8.12 Event Input Control
Name: EVCTRL
Offset: 0x2C
Reset: 0x00000000
Property: PAC Write-Protection
Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0
consists of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT
registers, with a 0x80 address spacing. For example, the register address offset for the Data
Direction (DIR) register for group 0 (PA00 to PA31) is 0x00, and the register address offset for
the DIR register for group 1 (PB00 to PB31) is 0x80.
There are up to four input event pins for each PORT group. Each byte of this register addresses one
Event input pin.
Bit 31 30 29 28 27 26 25 24
PORTEIx EVACTx[1:0] PIDx[4:0]
Access
RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
PORTEIx EVACTx[1:0] PIDx[4:0]
Access
RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
PORTEIx EVACTx[1:0] PIDx[4:0]
Access
RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
PORTEIx EVACTx[1:0] PIDx[4:0]
Access
RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bits 31,23,15,7 – PORTEIx PORT Event Input Enable x [x = 3..0]
Value Description
0
The event action x (EVACTx) will not be triggered on any incoming event.
1
The event action x (EVACTx) will be triggered on any incoming event.
Bits 30:29, 22:21,14:13,6:5 – EVACTx PORT Event Action x [x = 3..0]
These bits define the event action the PORT will perform on event input x. See also Table 32-4.
Bits 28:24,20:16,12:8,4:0 – PIDx PORT Event Pin Identifier x [x = 3..0]
These bits define the I/O pin on which the event action will be performed, according to Table 32-5.
SAM D5x/E5x Family Data Sheet
PORT - I/O Pin Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 907