Datasheet

11.10.1 Cache Type
Name: TYPE
Offset: 0x00
Reset: 0x000012D2
Property: R
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
CLSIZE[2:0] CSIZE[2:0]
Access
R R R R R R
Reset 0 1 0 0 1 0
Bit 7 6 5 4 3 2 1 0
LCKDOWN WAYNUM[1:0] RRP LRUP RANDP GCLK AP
Access
R R R R R R R R
Reset 1 1 0 1 0 0 1 0
Bits 13:11 – CLSIZE[2:0] Cache Line Size
This field configures the Cache Line Size.
Value Name Description
0x2
CLSIZE_16B Cache Line Size is 16 bytes
0x3-0x7
- Reserved
Bits 10:8 – CSIZE[2:0] Cache Size
This bit field configures the cache size.
Value Name Description
0x0
CSIZE_1KB Cache Size is 1 KB
0x1
CSIZE_2KB Cache Size is 2 KB
0x2
CSIZE_4KB Cache Size is 4 KB
0x3-0x7
- Reserved
Bit 7 – LCKDOWN Lock Down Supported
Writing a '0' to this bit disables the Lock Down feature.
Writing a '1' to this bit enables the Lock Down feature.
Value Description
0
Lock Down feature is not supported.
1
Lock Down feature is supported.
SAM D5x/E5x Family Data Sheet
CMCC - Cortex M Cache Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 90