Datasheet

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Offset Name Bit Pos.
0x24 CTRL
7:0 SAMPLING[7:0]
15:8 SAMPLING[15:8]
23:16 SAMPLING[23:16]
31:24 SAMPLING[31:24]
0x28 WRCONFIG
7:0 PINMASK[7:0]
15:8 PINMASK[15:8]
23:16 DRVSTR PULLEN INEN PMUXEN
31:24 HWSEL WRPINCFG WRPMUX PMUX[3:0]
0x2C EVCTRL
7:0 PORTEIx EVACTx[1:0] PIDx[4:0]
15:8 PORTEIx EVACTx[1:0] PIDx[4:0]
23:16 PORTEIx EVACTx[1:0] PIDx[4:0]
31:24 PORTEIx EVACTx[1:0] PIDx[4:0]
0x30 PMUX0 7:0 PMUXO[3:0] PMUXE[3:0]
...
0x3F PMUX15 7:0 PMUXO[3:0] PMUXE[3:0]
0x40 PINCFG0 7:0 DRVSTR PULLEN INEN PMUXEN
...
0x5F PINCFG31 7:0 DRVSTR PULLEN INEN PMUXEN
32.8 Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the
8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be
accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC
write protection is denoted by the "PAC Write-Protection" property in each individual register description.
For details, refer to 32.5.8 Register Access Protection.
SAM D5x/E5x Family Data Sheet
PORT - I/O Pin Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 893