Datasheet

• Output (OUT): I/O pin will be set when the incoming event has a high level ('1') and cleared when the
incoming event has a low-level ('0').
• Set (SET): I/O pin will be set when an incoming event is detected.
• Clear (CLR): I/O pin will be cleared when an incoming event is detected.
• Toggle (TGL): I/O pin will toggle when an incoming event is detected.
The event is output to pin without any internal latency. For SET, CLEAR and TOGGLE event actions, the
action will be executed up to three clock cycles after a rising edge.
The event actions can be configured with the Event Action m bit group in the Event Input Control
register( EVCTRL.EVACTm). Writing a '1' to a PORT Event Enable Input m of the Event Control register
(EVCTRL.PORTEIm) enables the corresponding action on input event. Writing '0' to this bit disables the
corresponding action on input event. Note that several actions can be enabled for incoming events. If
several events are connected to the peripheral, any enabled action will be taken for any of the incoming
events. Refer to EVSYS – Event System. for details on configuring the Event System.
Each event input can address one and only one I/O pin at a time. The selection of the pin is indicated by
the PORT Event Pin Identifier of the Event Input Control register (EVCTR.PIDn). On the other hand, one
I/O pin can be addressed by up to four different input events. To avoid action conflict on the output value
of the register (OUT) of this particular I/O pin, only one action is performed according to the table below.
Note that this truth table can be applied to any SET/CLR/TGL configuration from two to four active input
events.
Table 32-3. Priority on Simultaneous SET/CLR/TGL Event Actions
EVACT0 EVACT1 EVACT2 EVACT3 Executed Event Action
SET SET SET SET SET
CLR CLR CLR CLR CLR
All Other Combinations TGL
Be careful when the event is output to pin. Due to the fact the events are received asynchronously, the
I/O pin may have unpredictable levels, depending on the timing of when the events are received. When
several events are output to the same pin, the lowest event line will get the access. All other events will
be ignored.
Related Links
31. EVSYS – Event System
32.6.5 PORT Access Priority
The PORT is accessed by different systems:
• The ARM
®
CPU through the high-speed matrix and the AHB/APB bridge (APB)
• EVSYS through four asynchronous input events
The following priority is adopted:
1. APB
2. EVSYS input events, except for events with EVCTRL.EVACTn=OUT, where the output pin directly
follows the event input signal, independently of the OUT register value.
For input events that require different actions on the same I/O pin, refer to 32.6.4 Events.
SAM D5x/E5x Family Data Sheet
PORT - I/O Pin Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 891