Datasheet

has control over the Output state of the pad, as well as the ability to read the current Physical Pad state.
Refer to I/O Multiplexing and Considerations for details.
Device-specific configurations may cause some lines (and the corresponding Pxy pin) not to be
implemented.
Related Links
6. I/O Multiplexing and Considerations
32.5.2 Power Management
During Reset, all PORT lines are configured as inputs with input buffers, output buffers and pull disabled.
When the device is set to the BACKUP sleep mode, even if the PORT configuration registers and input
synchronizers will lose their contents (these will not be restored when PORT is powered up again), the
latches in the pads will keep their current configuration, such as the output value and pull settings. Refer
to the Power Manager documentation for more features related to the I/O lines configuration in and out of
BACKUP mode.
The PORT peripheral will continue operating in any Sleep mode where its source clock is running.
Related Links
18.6.3.4 I/O Lines Retention in HIBERNATE or BACKUP Mode
32.5.3 Clocks
The PORT bus clock (CLK_PORT_APB) can be enabled and disabled in the Main Clock module, and the
default state of CLK_PORT_APB can be found in the Peripheral Clock Masking section in MCLK – Main
Clock.
The PORT requires an APB clock, which may be divided from the CPU main clock and allows the CPU to
access the registers of PORT through the high-speed matrix and the AHB/APB bridge.
One clock cycle latency can be observed on the APB access in case of concurrent PORT accesses.
Related Links
15. MCLK – Main Clock
32.5.4 DMA
Not applicable.
32.5.5 Interrupts
Not applicable.
32.5.6 Events
The events of this peripheral are connected to the Event System.
The output of an event to a pin through PORT is always asynchronous. This must be configured in the
Event System by writing ASYNCHRONOUS to the Path Selection bits in the respective Channel n Control
register of the Event System (EVSYS.CHANNELn.PATH).
Related Links
31. EVSYS – Event System
32.5.7 Debug Operation
When the CPU is halted in Debug mode, this peripheral will continue normal operation.
SAM D5x/E5x Family Data Sheet
PORT - I/O Pin Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 885