Datasheet

32.3 Block Diagram
Figure 32-1. PORT Block Diagram
ANALOG
BLOCKS
PERIPHERALS
Digital Controls of Analog Blocks
Analog Pad
Connections
I/O
PADS
Port Line
Bundles
IP Line Bundles
Peripheral Mux Select
PORT
Control
and
Status
Pad Line
Bundles
PORTMUX
32.4 Signal Description
Table 32-1. Signal Description for PORT
Signal name Type Description
Pxy Digital I/O General purpose I/O pin y in group x
Refer to the I/O Multiplexing and Considerations for details on the pin mapping for this peripheral. One
signal can be mapped on several pins.
Related Links
6. I/O Multiplexing and Considerations
32.5 Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly as follows.
32.5.1 I/O Lines
The I/O lines of the PORT are mapped to pins of the physical device. The following naming scheme is
used:
Each line bundle with up to 32 lines is assigned an identifier 'xy', with letter x=A, B, C… and two-digit
number y=00, 01, …31. Examples: A24, C03.
PORT pins are labeled 'Pxy' accordingly, for example PA24, PC03. This identifies each pin in the device
uniquely.
Each pin may be controlled by one or more peripheral multiplexer settings, which allows the pad to be
routed internally to a dedicated peripheral function. When the setting is enabled, the selected peripheral
SAM D5x/E5x Family Data Sheet
PORT - I/O Pin Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 884