Datasheet

31.7.9 Channel n Interrupt Enable Clear
Name: CHINTENCLR
Offset: 0x24 + n*0x08 [n=0..31]
Reset: 0x00
Property: PAC Write-Protection
Bit 7 6 5 4 3 2 1 0
EVD OVR
Access
RW RW
Reset 0 0
Bit 1 – EVD Channel Event Detected Interrupt Disable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Event Detected Channel Interrupt Enable bit, which disables the Event
Detected Channel interrupt.
Value Description
0
The Event Detected Channel interrupt is disabled.
1
The Event Detected Channel interrupt is enabled.
Bit 0 – OVR Channel Overrun Interrupt Disable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Overrun Channel Interrupt Enable bit, which disables the Overrun
Channel interrupt.
Value Description
0
The Overrun Channel interrupt is disabled.
1
The Overrun Channel interrupt is enabled.
SAM D5x/E5x Family Data Sheet
EVSYS – Event System
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 876