Datasheet

31.7.8 Channel n Control
Name: CHANNEL
Offset: 0x20 + n*0x08 [n=0..31]
Reset: 0x00008000
Property: PAC Write-Protection
This register allows the user to configure channel n. To write to this register, do a single, 32-bit write of all
the configuration data.
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
ONDEMAND RUNSTDBY EDGSEL[1:0] PATH[1:0]
Access
RW RW RW RW RW RW
Reset 1 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
EVGEN[7:0]
Access
RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bit 15 – ONDEMAND Generic Clock On Demand
Value Description
0
Generic clock for a channel is always on, if the channel is configured and generic clock
source is enabled.
1
Generic clock is requested on demand while an event is handled
Bit 14 – RUNSTDBY Run in Standby
This bit is used to define the behavior during standby sleep mode.
Value Description
0
The channel is disabled in standby sleep mode.
1
The channel is not stopped in standby sleep mode and depends on the
CHANNEL.ONDEMAND bit.
Bits 11:10 – EDGSEL[1:0] Edge Detection Selection
These bits set the type of edge detection to be used on the channel.
These bits must be written to zero when using the asynchronous path.
Value Name Description
0x0
NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path
0x1
RISING_EDGE Event detection only on the rising edge of the signal from the event
generator
SAM D5x/E5x Family Data Sheet
EVSYS – Event System
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 872