Datasheet

31.7.3 Priority Control
Name: PRICTRL
Offset: 0x08
Reset: 0x00
Property: PAC Write-Protection
Bit 7 6 5 4 3 2 1 0
RREN PRI[4:0]
Access
RW RW RW RW RW RW
Reset 0 0 0 0 0 0
Bit 7 – RREN Round-Robin Scheduling Enable
For details on scheduling schemes, refer to Interrupt Status and Interrupts Arbitration
Value Description
0
Static scheduling scheme for channels with level priority
1
Round-robin scheduling scheme for channels with level priority
Bits 4:0 – PRI[4:0] Channel Priority Number
When round-robin arbitration is enabled (PRICTRL.RREN=1) for priority level, this register holds the
channel number of the last EVSYS channel being granted access as the active channel with priority level.
The value of this bit group is updated each time the INTPEND or any of CHINTFLAG registers are
written.
When static arbitration is enabled (PRICTRL.RREN=0) for priority level, and the value of this bit group is
nonzero, it will not affect the static priority scheme.
This bit group is not reset when round-robin scheduling gets disabled (PRICTRL.RREN written to zero).
SAM D5x/E5x Family Data Sheet
EVSYS – Event System
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 866