Datasheet

...........continued
Offset Name Bit Pos.
0x0108 CHANNEL29
7:0 EVGEN[7:0]
15:8 ONDEMAND RUNSTDBY EDGSEL[1:0] PATH[1:0]
23:16
31:24
0x010C CHINTENCLR29 7:0 EVD OVR
0x010D CHINTENSET29 7:0 EVD OVR
0x010E CHINTFLAG29 7:0 EVD OVR
0x010F CHSTATUS29 7:0 BUSYCH RDYUSR
0x0110 CHANNEL30
7:0 EVGEN[7:0]
15:8 ONDEMAND RUNSTDBY EDGSEL[1:0] PATH[1:0]
23:16
31:24
0x0114 CHINTENCLR30 7:0 EVD OVR
0x0115 CHINTENSET30 7:0 EVD OVR
0x0116 CHINTFLAG30 7:0 EVD OVR
0x0117 CHSTATUS30 7:0 BUSYCH RDYUSR
0x0118 CHANNEL31
7:0 EVGEN[7:0]
15:8 ONDEMAND RUNSTDBY EDGSEL[1:0] PATH[1:0]
23:16
31:24
0x011C CHINTENCLR31 7:0 EVD OVR
0x011D CHINTENSET31 7:0 EVD OVR
0x011E CHINTFLAG31 7:0 EVD OVR
0x011F CHSTATUS31 7:0 BUSYCH RDYUSR
0x0120 USER0
7:0 CHANNEL[7:0]
15:8
23:16
31:24
...
0x0228 USER66
7:0 CHANNEL[7:0]
15:8
23:16
31:24
31.7 Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition,
the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be
accessed directly.
Optional write protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write
Protection" property in each individual register description.
Refer to Register Access Protection and PAC - Peripheral Access Controller.
Related Links
27. PAC - Peripheral Access Controller
SAM D5x/E5x Family Data Sheet
EVSYS – Event System
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 862