Datasheet

11.6.7 Tightly Coupled Memory
Users can use a part of the cache as Tightly Coupled Memory (TCM). The cache size is determined by
the Cache Size Configuration by Software bits in the Cache Configuration register (CFG.CSIZESW). The
relation between cache and TCM is as given below:
TCM size = maximum Cache size - configured Cache size.
The TCM start address can be obtained from the product memory mapping. The cache memory starts
first from the address followed by the TCM memory. Size of the Way is fixed and the number of ways
varies according to the available size for the cache memory. For additional information, refer to the
section Product Memory Mapping.
Table 11-1. TCM Sizes
Max. Cache Configured Cache TCM Size
4 KB 4 KB 0 KB
4 KB 1 KB 3 KB
4 KB 2 KB 2 KB
4 KB 0 KB 4 KB
The TCM is also accessible in its maximum size when the CMCC is disabled. The TCM does not need to
be locked in order to operate.
Note: Writing into the cache DATA RAM region through the CPU can overwrite the valid cache lines.
This can result in data corruption when the cache controller is accessing the data for cache transactions.
Access the DATA RAM region only after configuring it as TCM.
11.6.8 Cache Maintenance
11.6.8.1 Cache Invalidate by Line Operation
When an invalidate by line command is issued, the CMCC resets the valid bit information of the decoded
cache line. As the line is no longer valid, the replacement counter points to that line.
• Disable the cache controller by writing a zero to the Cache Controller Enable bit in the Cache Control
register (CTRL.CEN).
• Check SR.CSTS to verify that the CMCC is successfully disabled.
• Perform an invalidate by line by writing the set {index,way} in the Cache Maintenance 1 register
(MAINT1.INDEX, MAINT1.WAY).
• Enable the CMCC by writing a '1' to CTRL.CEN.
11.6.8.2 Cache Invalidate All Operation
Use the following sequence to invalidate all cache entries.
• Disable the cache controller by writing a zero to the Cache Enable bit in the Cache Control register
(CTRL.CEN).
• Check SR.CSTS to verify that the CMCC is successfully disabled.
• Perform a full invalidate operation by writing a '1' to the Cache Controller Invalidate All bit in the
Cache Maintenance 0 register (MAINT0.INVALL).
• Enable the CMCC by writing a '1' to CTRL.CEN.
SAM D5x/E5x Family Data Sheet
CMCC - Cortex M Cache Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 85