Datasheet

Important: Only EVSYS channel 0 to 11 can be configured as synchronous or resynchronized.
Related Links
15.6.2.6 Peripheral Clock Masking
14. GCLK - Generic Clock Controller
31.4.4 DMA
Not applicable.
31.4.5 Interrupts
The interrupt request line is connected to the interrupt controller. Using the EVSYS interrupts requires the
interrupt controller to be configured first. Refer to Nested Vector Interrupt Controller for details.
Related Links
10.2 Nested Vector Interrupt Controller
31.4.6 Events
Not applicable.
31.4.7 Debug Operation
When the CPU is halted in Debug mode, this peripheral will continue normal operation. If the peripheral is
configured to require periodical service by the CPU through interrupts or similar, improper operation or
data loss may result during debugging. This peripheral can be forced to halt operation during debugging.
31.4.8 Register Access Protection
Registers with write access can be optionally write-protected by the Peripheral Access Controller (PAC),
except for the following:
• Channel Pending Interrupt (INTPEND)
• Channel n Interrupt Flag Status and Clear (CHINTFLAGn)
Note: Optional write protection is indicated by the "PAC Write Protection" property in the register
description.
Write protection does not apply for accesses through an external debugger.
31.4.9 Analog Connections
Not applicable.
31.5 Functional Description
31.5.1 Principle of Operation
The Event System consists of several channels which route the internal events from peripherals
(generators) to other internal peripherals or I/O pins (users). Each event generator can be selected as
source for multiple channels, but a channel cannot be set to use multiple event generators at the same
time.
A channel path can be configured in asynchronous, synchronous or resynchronized mode of operation.
The mode of operation must be selected based on the requirements of the application.
SAM D5x/E5x Family Data Sheet
EVSYS – Event System
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 848