Datasheet

11.6.3 Change Cache Size
It is possible to change the cache size by writing to the Cache Size Configured By Software bits in the
Cache Configuration register (CFG.CSIZESW).
Use the following sequence to change the cache size:
• Disable the CMCC controller by writing a zero to the Cache Controller Enable bit in the Cache
Control register (CTRL.CEN=0).
• Check the Cache Controller Status bit in the Cache Status register to verify that the CMCC is
successfully disabled (SR.CSTS=0).
• Change CFG.CSIZESW to its new value.
• Enable the CMCC by writing CTRL.CEN=1.
11.6.4 Data Cache Disable
The Instructions alone can be cached by disabling the Data cache, as described in the following steps:
1. Disable the cache controller by writing a ‘0’ to CTRL.CEN.
2. Check SR.CSTS to verify whether the CMCC is successfully disabled.
3. Write CFG.DCDIS = 1.
4. Enable the CMCC by writing CTRL.CEN = 1.
11.6.5 Instruction Cache Disable
The Data alone can be cached by disabling the Instruction cache, as described in the following steps:
1. Disable the cache controller by writing CTRL.CEN = 0.
2. Check SR.CSTS to verify that the CMCC is successfully disabled.
3. Write CFG.ICDIS = 1.
4. Enable the CMCC by writing CTRL.CEN = 1.
11.6.6 Cache Load and Lock
It is possible to lock a specific way for code optimization by writing the Lock Way register
(LCKWAY.LCKWAY). The locked way will not be updated by the CMCC as part of cache operations.
The load and lock mechanism can be implemented to use cache memory in a deterministic way. Follow
these steps to load and lock a way:
1. Disable cache controller by clearing the CTRL.CEN bit.
2. Invalidate the desired WAY line by line. This will reset the round robin algorithm of the invalidated
line, that will become eligible for the next load operation.
3. Disable the Instruction cache, but keep the Data cache enabled.
4. Enable the cache by setting the CTRL.CEN bit.
5. Place the respective piece of code and/or data to the corresponding WAY due to simple LOAD
operations. Loading the piece of code and/or data will force the cache to refill the previous
invalidated line in the right way. No need to load all the bytes of the line, only the first byte. The
cache will automatically refill the complete line.
6. Lock the specific WAY by setting LCKWAY.LCKWAY[3:0].
7. Re-enable the instruction cache. The locked WAY is now loaded and ready to operate. The
remaining WAYS can be used as I-cache or D-cache as required.
SAM D5x/E5x Family Data Sheet
CMCC - Cortex M Cache Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 84