Datasheet

30.7 Register Summary
Offset Name Bit Pos.
0x00 CTRLA 7:0 ENABLE SWRST
0x01 CTRLB 7:0 START
0x02 CFGA
7:0 REFNUM[7:0]
15:8
0x04
...
0x07
Reserved
0x08 INTENCLR 7:0 DONE
0x09 INTENSET 7:0 DONE
0x0A INTFLAG 7:0 DONE
0x0B STATUS 7:0 OVF BUSY
0x0C SYNCBUSY
7:0 ENABLE SWRST
15:8
23:16
31:24
0x10 VALUE
7:0 VALUE[7:0]
15:8 VALUE[15:8]
23:16 VALUE[23:16]
31:24
30.8 Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition,
the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be
accessed directly.
Some registers require synchronization when read and/or written. Synchronization is denoted by the
"Read-Synchronized" and/or "Write-Synchronized" property in each individual register description.
Some registers are enable-protected, meaning they can only be written when the module is disabled.
Enable protection is denoted by the "Enable-Protected" property in each individual register description.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC
write protection is denoted by the "PAC Write-Protection" property in each individual register description.
SAM D5x/E5x Family Data Sheet
FREQM – Frequency Meter
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 836