Datasheet

The FREQM is reset by writing a '1' to the Software Reset bit in the Control A register (CTRLA.SWRST).
On software reset, all registers in the FREQM will be reset to their initial state, and the FREQM will be
disabled.
Then ENABLE and SWRST bits are write-synchronized.
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30.6.7 Synchronization
30.6.2.3 Measurement
In the Configuration A register, the Number of Reference Clock Cycles field (CFGA.REFNUM) selects the
duration of the measurement. The measurement is given in number of GCLK_FREQM_REF periods.
Note: The REFNUM field must be written before the FREQM is enabled.
After the FREQM is enabled, writing a '1' to the START bit in the Control B register (CTRLB.START)
starts the measurement. The BUSY bit in Status register (STATUS.BUSY) is set when the measurement
starts, and cleared when the measurement is complete.
There is also an interrupt request for Measurement Done: When the Measurement Done bit in Interrupt
Enable Set register (INTENSET.DONE) is '1' and a measurement is finished, the Measurement Done bit
in the Interrupt Flag Status and Clear register (INTFLAG.DONE) will be set and an interrupt request is
generated.
The result of the measurement can be read from the Value register (VALUE.VALUE). The frequency of
the measured clock GCLK_FREQM_MSR is then:

CLK_MSR
=
VALUE
REFNUM

CLK_REF
Note: In order to make sure the measurement result (VALUE.VALUE[23:0]) is valid, the overflow status
(STATUS.OVF) should be checked.
In case an overflow condition occurred, indicated by the Overflow bit in the STATUS register
(STATUS.OVF), either the number of reference clock cycles must be reduced (CFGA.REFNUM), or a
faster reference clock must be configured. Once the configuration is adjusted, clear the overflow status by
writing a '1' to STATUS.OVF. Then another measurement can be started by writing a '1' to CTRLB.START.
30.6.3 DMA Operation
Not applicable.
30.6.4 Interrupts
The FREQM has one interrupt source:
• DONE: A frequency measurement is done.
The interrupt flag in the Interrupt Flag Status and Clear (30.8.6 INTFLAG) register is set when the
interrupt condition occurs. The interrupt can be enabled by writing a '1' to the corresponding bit in the
Interrupt Enable Set (30.8.5 INTENSET) register, and disabled by writing a '1' to the corresponding bit in
the Interrupt Enable Clear (30.8.4 INTENCLR) register.
An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled.
The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, or the
FREQM is reset. See 30.8.6 INTFLAG for details on how to clear interrupt flags. All interrupt requests
from the peripheral are ORed together on system level to generate one combined interrupt request to the
NVIC. The user must read the 30.8.6 INTFLAG register to determine which interrupt condition is present.
SAM D5x/E5x Family Data Sheet
FREQM – Frequency Meter
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 834