Datasheet

11.4 Signal Description
Not applicable.
11.5 Product Dependencies
Not applicable.
11.5.1 I/O Lines
Not applicable.
11.5.2 Power Management
The CMCC will continue to function as long as the CPU is not sleeping and CMCC is enabled.
11.5.3 Clocks
Not applicable.
11.5.4 DMA
Not applicable.
11.5.5 Interrupts
Not applicable.
11.5.6 Events
Not applicable.
11.5.7 Debug Operation
When the CPU is halted in debug mode, the CMCC is halted. Any read access by the debugger in
cached zones are not cached.
11.5.8 Register Access Protection
Not applicable.
11.5.9 Analog Connections
Not applicable.
11.6 Functional Description
11.6.1 Principle of Operation
11.6.2 Initialization and Normal Operation
On reset, the cache controller data entries are all invalidated, and the cache is disabled. The cache is
transparent to processor operations. The cache controller is activated through the use of its configuration
registers. The configuration interface is memory mapped in the APB bus.
Use the following sequence to enable the cache controller:
• Verify that the CMCC is disabled, reading the value of the SR.CSTS.
• Enable the CMCC by writing '1' in CTRL.CEN. The MODULE is disabled by writing a '0' in
CTRL.CEN.
SAM D5x/E5x Family Data Sheet
CMCC - Cortex M Cache Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 83