Datasheet

29.8.7 Clock Failure Detector Control
Name: CFDCTRL
Offset: 0x16
Reset: 0x00
Property: PAC Write-Protection
Bit 7 6 5 4 3 2 1 0
CFDPRESC SWBACK CFDEN
Access
R/W R/W R/W
Reset 0 0 0
Bit 2 – CFDPRESC Clock Failure Detector Prescaler
This bit selects the prescaler for the Clock Failure Detector.
Value Description
0
The CFD safe clock frequency is the OSCULP32K frequency
1
The CFD safe clock frequency is the OSCULP32K frequency divided by 2
Bit 1 – SWBACK Clock Switch Back
This bit clontrols the XOSC32K output switch back to the external clock or crystal scillator in case of clock
recovery.
Value Description
0
The clock switch is disabled.
1
The clock switch is enabled. This bit is reset when the XOSC32K output is switched back to
the external clock or crystal oscillator.
Bit 0 – CFDEN Clock Failure Detector Enable
This bit selects the Clock Failure Detector state.
Value Description
0
The CFD is disabled.
1
The CFD is enabled.
SAM D5x/E5x Family Data Sheet
OSC32KCTRL – 32KHz Oscillators Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 828