Datasheet

29.7 Register Summary
Offset Name Bit Pos.
0x00 INTENCLR
7:0
XOSC32KFAI
L
XOSC32KRD
Y
15:8
23:16
31:24
0x04 INTENSET
7:0
XOSC32KFAI
L
XOSC32KRD
Y
15:8
23:16
31:24
0x08 INTFLAG
7:0
XOSC32KFAI
L
XOSC32KRD
Y
15:8
23:16
31:24
0x0C STATUS
7:0 XOSC32KSW
XOSC32KFAI
L
XOSC32KRD
Y
15:8
23:16
31:24
0x10 RTCCTRL 7:0 RTCSEL[2:0]
0x11
...
0x13
Reserved
0x14 XOSC32K
7:0 ONDEMAND RUNSTDBY EN1K EN32K XTALEN ENABLE
15:8 CGM[1:0] WRTLOCK STARTUP[2:0]
0x16 CFDCTRL 7:0 CFDPRESC SWBACK CFDEN
0x17 EVCTRL 7:0 CFDEO
0x18
...
0x1B
Reserved
0x1C OSCULP32K
7:0 EN1K EN32K
15:8 WRTLOCK CALIB[5:0]
23:16
31:24
29.8 Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition,
the 8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be
accessed directly.
All registers with write-access can be write-protected optionally by the peripheral access controller (PAC).
Optional Write-Protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write-
SAM D5x/E5x Family Data Sheet
OSC32KCTRL – 32KHz Oscillators Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 819