Datasheet

Event
If the Event Output Enable bit in the Event Control register (EVCTRL.CFDEO) is set, the CFD clock
failure will be output on the Event Output. When the CFD is switched to the safe clock, the CFD clock
failure will not be output on the Event Output.
Sleep Mode
The CFD is halted depending on configuration of the XOSC32K and the peripheral clock request. For
further details, refer to the Sleep Behavior table above. The CFD interrupt can be used to wake up the
device from sleep modes.
29.6.4 32 kHz Ultra Low-Power Internal Oscillator (OSCULP32K) Operation
The OSCULP32K provides a tunable, low-speed, and ultra low-power clock source. The OSCULP32K is
factory-calibrated under typical voltage and temperature conditions.
The OSCULP32K is enabled by default after a Power-on Reset (POR), and will always run except during
POR. The frequency of the OSCULP32K Oscillator is controlled by the value in the Calibration bits in the
32 kHz Ultra Low-Power Internal Oscillator Control register (OSCULP32K.CALIB). This data is used to
compensate for process variations.
OSCULP32K.CALIB is automatically loaded from Flash Factory Calibration during start-up. The
calibration value can be overridden by the user by writing to OSCULP32K.CALIB.
Users can lock the OSCULP32K configuration by setting the Write Lock bit in the 32 kHz Ultra Low-Power
Internal Oscillator Control register (OSCULP32K.WRTLOCK = 1). If set, the OSCULP32K configuration is
locked until POR is detected.
The OSCULP32K can be used as a source for Generic Clock Generators (GCLK) or for the Real-Time
Counter (RTC). To ensure proper operation, the GCLK or RTC modules must be disabled before the
clock selection is changed.
Related Links
21. RTC – Real-Time Counter
29.6.6 Real-Time Counter Clock Selection
14. GCLK - Generic Clock Controller
29.6.5 Watchdog Timer Clock Selection
The Watchdog Timer (WDT) uses the internal 1.024kHz OSCULP32K output clock. This clock is running
all the time and internally enabled when requested by the WDT module.
Related Links
20. WDT – Watchdog Timer
29.6.6 Real-Time Counter Clock Selection
Before enabling the RTC module, the RTC clock must be selected first. All oscillator outputs are valid as
RTC clock. The selection is done in the RTC Control register (RTCCTRL). To ensure a proper operation,
it is highly recommended to disable the RTC module first, before the RTC clock source selection is
changed.
Related Links
21. RTC – Real-Time Counter
29.6.7 Interrupts
The OSC32KCTRL has the following interrupt sources:
SAM D5x/E5x Family Data Sheet
OSC32KCTRL – 32KHz Oscillators Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 817