Datasheet

Table Of Contents

11. CMCC - Cortex M Cache Controller

11.1 Overview

The Cortex M Cache Controller provides an L1 cache to the Cortex M CPU. The CMCC sits transparently

between the CPU and the cache leading to improved performance.

The CMCC interfaces with the CPU through the AHB, and is connected to the APB bus interface for its

configuration.

11.2 Features

• Physically addressed and physically tagged

• L1 data and instruction cache set to 4 KB

• L1 cache line size set to 16 Bytes

• L1 cache integrates 32-bit bus master interface

• Unified 4-Way set associative cache architecture

• Lock-Down feature, which allows cached to be locked per way

• Write through cache operations, read allocate

• Configurable as data and instruction Tightly Coupled Memory (TCM)

• Round Robin victim selection policy

• Event Monitoring, with one programmable 32-bit counter

• Cache Interface includes cache maintenance operations registers

SAM D5x/E5x Family Data Sheet

CMCC - Cortex M Cache Controller

Datasheet

DS60001507E-page 81