Datasheet

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DCOFILTER[2:0] Capacitor (pF) Bandwidth Fn (MHz)
0x5 3 0.55
0x6 3.5 0.45
0x7 4 0.4
Bit 11 – LBYPASS Lock Bypass
Bits 10:8 – LTIME[2:0] Lock Time
Write these bits to select the lock time-out value, as shown in the figure below:
Value Name Description
0x0
Default No time-out. Automatic lock.
0x1
Reserved
0x2
Reserved
0x3
Reserved
0x4
800US Time-out if no lock within 800 us
0x5
900US Time-out if no lock within 900 us
0x6
1MS Time-out if no lock within 1 ms
0x7
1P1MS Time-out if no lock within 1.1 ms
Bits 7:5 – REFCLK[2:0] Reference Clock Selection
Write these bits to select the DPLLn clock reference, as shown in the table below:
Value Name Description
0x0
GCLK Dedicated GCLK clock reference
0x1
XOSC32 XOSC32K clock reference (default)
0x2
XOSC0 XOSC0 clock reference
0x3
XOSC1 XOSC1 clock reference
Other
- Reserved
Bit 4 – WUF Wake Up Fast
0: DPLLn clock is output after startup and lock time.
1: DPLLn clock is output after startup time.
Bits 3:0 – FILTER[3:0] Proportional Integral Filter Selection
These bits select the DPLLn digital filter type, as shown in the table below:
Table 28-9. Proportional Integral Filter selection
FILTER[3:0] PLL Bandwidth (fn) Damping Factor
0x0 92.7 kHz 0.76
0x1 131 kHz 1.08
0x2 46.4 kHz 0.38
0x3 65.6 kHz 0.54
0x4 131 kHz 0.56
0x5 185 kHz 0.79
SAM D5x/E5x Family Data Sheet
OSCCTRL – Oscillators Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 807