Datasheet

28.8.14 DPLL Control B
Name: DPLLCTRLB
Offset: 0x38 + n*0x14 [n=0..1]
Reset: 0x00000020
Property: PAC Write-Protection, Enable-Protected
Bit 31 30 29 28 27 26 25 24
DIV[10:8]
Access
R/W R/W R/W
Reset 0 0 0
Bit 23 22 21 20 19 18 17 16
DIV[7:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
DCOEN DCOFILTER[2:0] LBYPASS LTIME[2:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
REFCLK[2:0] WUF FILTER[3:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 1 0 0 0 0 0
Bits 26:16 – DIV[10:0] Clock Divider
These bits are used to set the XOSC clock division factor and can be calculated with following formula:

DIV
=
XOSC
2 ×
DIV + 1
Bit 15 – DCOEN DCO Filter Enable
0: Disable DCO filter controller. Sigma-Delta DAC is automatically set the PLL itself.
1: Enable DCO filter controller. DCOFILTER[2:0] is used to select sigma-delta DAC filter bandwidth.
Bits 14:12 – DCOFILTER[2:0] Sigma-Delta DCO Filter Selection
These bits select the DPLLn sigma-delta DCO filter type, as shown in the table below:
Table 28-8. Sigma-delta DCO Filter selection
DCOFILTER[2:0] Capacitor (pF) Bandwidth Fn (MHz)
0x0 0.5 3.21
0x1 1 1.6
0x2 1.5 1.1
0x3 2 0.8
0x4 2.5 0.64
SAM D5x/E5x Family Data Sheet
OSCCTRL – Oscillators Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 806