Datasheet

28.8.12 DPLL Control A
Name: DPLLCTRLA
Offset: 0x30 + n*0x14 [n=0..1]
Reset: 0x80
Property: PAC Write-Protection, Write-Synchronized(ENABLE), Enable-Protected (ONDEMAND,
RUNSTDBY)
Bit 7 6 5 4 3 2 1 0
ONDEMAND RUNSTDBY ENABLE
Access
R/W R/W R/W
Reset 1 0 0
Bit 7 – ONDEMAND On Demand Control
The On Demand operation mode allows the DPLLn to be enabled or disabled, depending on peripheral
clock requests.
If On Demand is set, the DPLLn will be running only when requested by a peripheral and enabled
(DPLLnCTRLA. ENABLE=1). If there is no peripheral requesting the DPLLn’s clock source, the DPLLn
will be in a disabled state.
If On Demand is cleared, the DPLLn will always be running when enabled (DPLLnCTRLA.ENABLE=1).
In standby sleep mode, the On Demand operation is still active.
0: The DPLLn is always running.
1: The DPLLn is running when a peripheral is requesting the DPLLn to be used as a clock source. The
DPLLn is not running if no peripheral is requesting the clock source.
Bit 6 – RUNSTDBY Run in Standby
This bit controls how the DPLLn behaves during standby sleep mode:
0: The DPLLn is not running in standby sleep mode if no peripheral requests the clock.
1: The DPLLn is running in standby sleep mode. If ONDEMAND is one, the DPLLn will be running when a
peripheral is requesting the clock. If ONDEMAND is zero, the clock source will always be running in
standby sleep mode.
Bit 1 – ENABLE DPLL Enable
0: The DPLLn is disabled.
1: The DPLLn is enabled.
The software operation of enabling or disabling the DPLLn takes a few clock cycles, so the
DPLLnSYNCBUSY. ENABLE status bit indicates when the DPLLn is successfully enabled or disabled.
SAM D5x/E5x Family Data Sheet
OSCCTRL – Oscillators Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 804