Datasheet

28.8.9 DFLL48M Value
Name: DFLLVAL
Offset: 0x24
Reset: 0x0000XXXX
Property: PAC Write-Protection, Read-Synchronized, Write-Synchronized
Bit 31 30 29 28 27 26 25 24
DIFF[15:8]
Access
R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
DIFF[7:0]
Access
R R R R R R R R
Reset 0 0 0 0 0 0 0 x
Bit 15 14 13 12 11 10 9 8
COARSE[5:0]
Access
R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 x
Bit 7 6 5 4 3 2 1 0
FINE[7:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 x
Bits 31:16 – DIFF[15:0] Multiplication Ratio Difference
In closed-loop mode (DFLLCTRLB.MODE is written to one), this bit group indicates the difference
between the ideal number of DFLL cycles and the counted number of cycles. This value is not updated in
open-loop mode, and should be considered invalid in that case.
Bits 15:10 – COARSE[5:0] Coarse Value
Set the value of the Coarse Calibration register. In closed-loop mode, this field is read-only.
The DFLL48M is factory-calibrated for 48MHz. Register DFLLVAL.COARSE stores the coarse frequency
calibration after reset.
Bits 7:0 – FINE[7:0] Fine Value
Set the value of the Fine Calibration register. In closed-loop mode, this field is read-only.
The DFLL48M is factory-calibrated for 48MHz. Register DFLLVAL.FINE stores the coarse frequency
calibration after reset.
SAM D5x/E5x Family Data Sheet
OSCCTRL – Oscillators Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 801