Datasheet

28.8.5 Status
Name: STATUS
Offset: 0x10
Reset: 0x00000000
Bit 31 30 29 28 27 26 25 24
DPLL1LDRTO DPLL1TO DPLL1LCKF DPLL1LCKR
Access
R R R R
Reset 0 0 0 0
Bit 23 22 21 20 19 18 17 16
DPLL0LDRTO DPLL0TO DPLL0LCKF DPLL0LCKR
Access
R R R R
Reset 0 0 0 0
Bit 15 14 13 12 11 10 9 8
DFLLRCS DFLLLCKC DFLLLCKF DFLLOOB DFLLRDY
Access
R R R R R
Reset 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
XOSCCKSW1 XOSCCKSW0 XOSCFAIL1 XOSCFAIL0 XOSCRDY1 XOSCRDY0
Access
R R R R R R/W
Reset 0 0 0 0 0 0
Bit 27 – DPLL1LDRTO DPLL1 Loop Divider Ratio Update Complete
0: DPLL1 Loop Divider Ratio Update Complete not detected.
1: DPLL1 Loop Divider Ratio Update Complete detected.
Bit 26 – DPLL1TO DPLL1 Lock Timeout
0: DPLL1 Lock time-out not detected.
1: DPLL1 Lock time-out detected.
Bit 25 – DPLL1LCKF DPLL1 Lock Fall
0: DPLL1 Lock fall edge not detected.
1: DPLL1 Lock fall edge detected.
Bit 24 – DPLL1LCKR DPLL1 Lock Rise
0: DPLL1 Lock rise edge not detected.
1: DPLL1 Lock rise edge detected.
Bit 19 – DPLL0LDRTO DPLL0 Loop Divider Ratio Update Complete
0: DPLL0 Loop Divider Ratio Update Complete not detected.
1: DPLL0 Loop Divider Ratio Update Complete detected.
Bit 18 – DPLL0TO DPLL0 Lock Timeout
0: DPLL0 Lock time-out not detected.
1: DPLL0 Lock time-out detected.
SAM D5x/E5x Family Data Sheet
OSCCTRL – Oscillators Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 792