Datasheet

Bit 10 – DFLLLCKF DFLL Lock Fine
This flag is cleared by writing a '1' to it.
This flag is set on a zero-to-one transition of the DFLL Lock Fine bit in the Status register
(STATUS.DFLLLCKF) and will generate an interrupt request if INTENSET.DFLLLCKF is '1'.
Writing a zero to this bit has no effect.
Writing a '1' to this bit clears the DFLL Lock Fine interrupt flag.
Bit 9 – DFLLOOB DFLL Out Of Bounds
This flag is cleared by writing a '1' to it.
This flag is set on a zero-to-one transition of the DFLL Out Of Bounds bit in the Status register
(STATUS.DFLLOOB) and will generate an interrupt request if INTENSET.DFLLOOB is '1'.
Writing a zero to this bit has no effect.
Writing a '1' to this bit clears the DFLL Out Of Bounds interrupt flag.
Bit 8 – DFLLRDY DFLL Ready
This flag is cleared by writing a '1' to it.
This flag is set on a zero-to-one transition of the DFLL Ready bit in the Status register
(STATUS.DFLLRDY) and will generate an interrupt request if INTENSET.DFLLRDY is '1'.
Writing a zero to this bit has no effect.
Writing a '1' to this bit clears the DFLL Ready interrupt flag.
Bit 2 – XOSCFAIL XOSCn Clock Failure
This flag is cleared by writing a '1' to it.
This flag is set on a zero-to-one transition of the XOSCn Clock Failure bit in the Status register
(STATUS.XOSCFAILn) and will generate an interrupt request if INTENSET.XOSCFAILn is '1'.
Writing a zero to this bit has no effect.
Writing a '1' to this bit clears the XOSCn Clock Failure interrupt flag.
Bits 0, 1 – XOSCRDY XOSCn Ready
This flag is cleared by writing a '1' to it.
This flag is set on a zero-to-one transition of the XOSC0 Ready bit in the Status register
(STATUS.XOSCRDYn) and will generate an interrupt request if INTENSET.XOSCRDYn is '1'.
Writing a zero to this bit has no effect.
Writing a '1' to this bit clears the XOSCn Ready interrupt flag.
SAM D5x/E5x Family Data Sheet
OSCCTRL – Oscillators Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 791