Datasheet

Bit 24 – DPLL1LCKR DPLL1 Lock Rise
This flag is cleared by writing a '1' to it.
This flag is set on a zero-to-one transition of the DPLL1 Lock Rise bit in the Status register (STATUS.
DPLL1LCKR) and will generate an interrupt request if INTENSET.DPLL1LCKR is '1'.
Writing a zero to this bit has no effect.
Writing a '1' to this bit clears the DPLL1 Lock Rise interrupt flag.
Bit 19 – DPLL0LDRTO DPLL0 Loop Divider Ratio Update Complete
This flag is cleared by writing a '1' to it.
This flag is set on a zero-to-one transition of the DPLL0 Loop Divider Ratio Update Complete bit in the
Status register (STATUS.DPLL0LDRTO) and will generate an interrupt request if
INTENSET.DPLL0LDRTO is '1'.
Writing a zero to this bit has no effect.
Writing a '1' to this bit clears the DPLL0 Loop Divider Ratio Update Complete interrupt flag.
Bit 18 – DPLL0LTO DPLL0 Lock Timeout
This flag is cleared by writing a '1' to it.
This flag is set on a zero-to-one transition of the DPLL0 Lock Timeout bit in the Status register (STATUS.
DPLL0LTO) and will generate an interrupt request if INTENSET.DPLL0LTO is '1'.
Writing a zero to this bit has no effect.
Writing a '1' to this bit clears the DPLL0 Lock Timeout interrupt flag.
Bit 17 – DPLL0LCKF DPLL0 Lock Fall
This flag is cleared by writing a '1' to it.
This flag is set on a zero-to-one transition of the DPLL0 Lock Fall bit in the Status register
(STATUS.DPLL0LCKF) and will generate an interrupt request if INTENSET.DPLL0LCKF is '1'.
Writing a zero to this bit has no effect.
Writing a '1' to this bit clears the DPLL0 Lock Fall interrupt flag.
Bit 16 – DPLL0LCKR DPLL0 Lock Rise
This flag is cleared by writing a '1' to it.
This flag is set on a zero-to-one transition of the DPLL0 Lock Rise bit in the Status register (STATUS.
DPLL0LCKR) and will generate an interrupt request if INTENSET.DPLL0LCKR is '1'.
Writing a zero to this bit has no effect.
Writing a '1' to this bit clears the DPLL0 Lock Rise interrupt flag.
Bit 12 – DFLLRCS DFLL Reference Clock Stopped
This flag is cleared by writing a '1' to it.
This flag is set on a zero-to-one transition of the DFLL Reference Clock Stopped bit in the Status register
(STATUS. DFLLRCS) and will generate an interrupt request if INTENSET.DFLLRCS is '1'.
Writing a zero to this bit has no effect.
Writing a '1' to this bit clears the DFLL Reference Clock Stopped interrupt flag.
Bit 11 – DFLLLCKC DFLL Lock Coarse
This flag is cleared by writing a '1' to it.
This flag is set on a zero-to-one transition of the DFLL Lock Coarse bit in the Status register
(STATUS.DFLLLCKC) and will generate an interrupt request if INTENSET.DFLLLCKC is '1'.
Writing a zero to this bit has no effect.
Writing a '1' to this bit clears the DFLL Lock Coarse interrupt flag.
SAM D5x/E5x Family Data Sheet
OSCCTRL – Oscillators Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 790