Datasheet

If a master is configured with QoS level DISABLE (0x0) or LOW (0x1) there will be a minimum latency of
one cycle for the RAM access.
The priority order for concurrent accesses are decided by two factors. First, the QoS level for the master
and second, a static priority given by the port ID. The lowest port ID has the highest static priority. See the
tables below for details.
The CPU QoS level can be written/read, using 32-bit access only, at address 0x4100C11C, bits [1:0]. Its
reset value is 0x3.
The ICM QoS level can be written/read, using 32-bit access only, at address 0x4100C128, bits [1:0]. Its
reset value is 0x1.
Refer to different master QOS control registers for configuring QoS for the other masters (DSU, DMAC,
CAN, USB).
Table 10-4. SRAM Port Connections QoS
SRAM Port
Connection
Port ID Connection Type QoS default QoS
CM4 - Cortex M4
Processor
0 Bus Matrix 0x4100C11C,
bits[1:0]
(1)
0x3
DSU - Device
Service Unit
1 Bus Matrix IP-CFG.LQOS 0x2
DMAC - Direct
Memory Access
Controller - Data
Access
2 (WR), 3 (RD) Bus Matrix IP-
PRICTRL0.QOSn
0x2
ICM - Integrity
Check Monitor
3 Bus Matrix 0x4100C128,
bits[1:0]
(1)
0x1
DMAC - Direct
Memory Access
Controller - Fetch
Access
4, 5 Direct IP-
PRICTRL0.QOSn
0x2
DMAC - Direct
Memory Access
Controller - Write-
Back Access
6, 7 Direct IP-
PRICTRL0.QOSn
0x2
SDHC0 - SD/MMC
Host Controller
8 Direct STATIC-1 0x1
SDHC1 - SD/MMC
Host Controller
9 Direct STATIC-1 0x1
CAN0 - Control
Area Network
10 Direct IP-MRCFG.QOS 0x1
CAN1 - Control
Area Network
11 Direct IP-MRCFG.QOS 0x1
SAM D5x/E5x Family Data Sheet
Processor and Architecture
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 79