Datasheet

28.8.4 Interrupt Flag Status and Clear
Name: INTFLAG
Offset: 0x0C
Reset: 0x00000000
Bit 31 30 29 28 27 26 25 24
DPLL1LDRTO DPLL1LTO DPLL1LCKF DPLL1LCKR
Access
R/W R/W R/W R/W
Reset 0 0 0 0
Bit 23 22 21 20 19 18 17 16
DPLL0LDRTO DPLL0LTO DPLL0LCKF DPLL0LCKR
Access
R/W R/W R/W R/W
Reset 0 0 0 0
Bit 15 14 13 12 11 10 9 8
DFLLRCS DFLLLCKC DFLLLCKF DFLLOOB DFLLRDY
Access
R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
XOSCFAIL XOSCRDY1 XOSCRDY0
Access
R/W R/W R/W
Reset 0 0 0
Bit 27 – DPLL1LDRTO DPLL1 Loop Divider Ratio Update Complete
This flag is cleared by writing a '1' to it.
This flag is set on a zero-to-one transition of the DPLL1 Loop Divider Ratio Update Complete bit in the
Status register (STATUS.DPLL1LDRTO) and will generate an interrupt request if
INTENSET.DPLL1LDRTO is '1'.
Writing a zero to this bit has no effect.
Writing a '1' to this bit clears the DPLL1 Loop Divider Ratio Update Complete interrupt flag.
Bit 26 – DPLL1LTO DPLL1 Lock Timeout
This flag is cleared by writing a '1' to it.
This flag is set on a zero-to-one transition of the DPLL1 Lock Timeout bit in the Status register (STATUS.
DPLL1LTO) and will generate an interrupt request if INTENSET.DPLL1LTO is '1'.
Writing a zero to this bit has no effect.
Writing a '1' to this bit clears the DPLL1 Lock Timeout interrupt flag.
Bit 25 – DPLL1LCKF DPLL1 Lock Fall
This flag is cleared by writing a '1' to it.
This flag is set on a zero-to-one transition of the DPLL1 Lock Fall bit in the Status register
(STATUS.DPLL1LCKF) and will generate an interrupt request if INTENSET.DPLL1LCKF is '1'.
Writing a zero to this bit has no effect.
Writing a '1' to this bit clears the DPLL1 Lock Fall interrupt flag.
SAM D5x/E5x Family Data Sheet
OSCCTRL – Oscillators Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 789