Datasheet

Table Of Contents

28.8.1 Event Control

Name: EVCTRL

Offset: 0x00

Reset: 0x00

Property: PAC Write-Protection

Bit 7 6 5 4 3 2 1 0

CFDEO1 CFDEO0

Access

R R R R R R R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 0, 1 – CFDEO Clock n Failure Detector Event Output Enable [n=0,1]

This bit indicates whether the XOSC Clock Failure detector event output is enabled or not and an output

event will be generated when the XOSC Clock Failure detector detects a clock failure.

0: Clock Failure detector event output is disabled and an event will not be generated.

1: Clock Failure detector event output is enabled and an event will be generated.

To prevent false event generation, the bit CFDEOn must be set or cleared only when the XOSCn is

disabled (XOSCCTRLn.ENABLE=0).

SAM D5x/E5x Family Data Sheet

OSCCTRL – Oscillators Controller

Datasheet

DS60001507E-page 782