Datasheet

Table Of Contents

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Offset Name Bit Pos.

0x54 DPLL1STATUS

7:0 CLKRDY LOCK

15:8

23:16

31:24

28.8 Register Description

Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition,

the 8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be

accessed directly.

Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection

is denoted by the "PAC Write-Protection" property in each individual register description. Refer to the

28.5.8 Register Access Protection section and the PAC - Peripheral Access Controller chapter for details.

Some registers require synchronization when read and/or written. Synchronization is denoted by the

"Read-Synchronized" or "Write-Synchronized" property in each individual register description. Refer to

the section on Synchronization for details.