Datasheet

...........continued
High-Speed Bus Matrix Masters Master ID
ICM - Integrity Check Monitor 6
DSU - Device Service Unit 7
Table 10-2. High-Speed Bus Matrix Slaves
High-Speed Bus Matrix Slaves Slave ID
Internal Flash Memory 0, 1
Smart EEPROM 2
SRAM Port 0 - CM4 Access 3
SRAM Port 1 - DSU Access 4
SRAM Port 2 - DMAC Data-Write Access 5
SRAM Port 3 - DMAC Data-Read and ICM Access 6
AHB-APB Bridge A 7
AHB-APB Bridge B 8
AHB-APB Bridge C 9
AHB-APB Bridge D 10
PUKCC 11
SDHC0 12
SDHC1 13
QSPI 14
BACKUP RAM Memory 15
10.3.3 SRAM Quality of Service
To ensure that masters with latency requirements get sufficient priority when accessing RAM, priority
levels can be assigned to the masters for different types of access.
The Quality of Service (QoS) level is independently selected for each master accessing the RAM. For any
access to the RAM, the RAM also receives the QoS level. The QoS levels and their corresponding bit
values for the QoS level configuration is shown in the table below.
Table 10-3. Quality of Service
Value Name Description
0x0 DISABLE Background (no sensitive
operation)
0x1 LOW Sensitive Bandwidth
0x2 MEDIUM Sensitive Latency
0x3 HIGH Critical Latency
SAM D5x/E5x Family Data Sheet
Processor and Architecture
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 78