Datasheet

Table Of Contents

28.6.9 Synchronization

Due to the multiple clock domains, some registers in the DFLL48M must be synchronized when

accessed. A register can require:

• Synchronization when written

• Synchronization when read

• No synchronization

When executing an operation that requires synchronization, the relevant synchronization bit in the

Synchronization Busy register (DFLLSYNC) will be set immediately, and cleared when synchronization is

complete.

The following registers need synchronization:

• ENABLE bit in DFLLCTRLA register - write-synchronized

• DFLLCTRLB register - read-synchronized

• DFLLVAL register - read- and write-synchronized

• DFLLMUL register - write-synchronized

Due to the multiple clock domains (XOSC32K, XOSC, GCLK and CK), some registers in the DPLL must

be synchronized when accessed. A register can require:

• Synchronization when written

• No synchronization

When executing an operation that requires synchronization, the relevant synchronization bit in the

Synchronization Busy register (DPLLnSYNCBUSY) will be set immediately, and cleared when

synchronization is complete.

The following bits need synchronization when written:

• Enable bit in control register A (DPLLnCTRLA.ENABLE)

• DPLLn Ratio register (DPLLnRATIO)

SAM D5x/E5x Family Data Sheet

OSCCTRL – Oscillators Controller

Datasheet

DS60001507E-page 778