Datasheet

Digital Filter Selection
The digital filter selection can be changed from the filter selection register DPLLnCTRLB.FILTER. The
DPLL digital filter coefficients are automatically adjusted in order to provide a good compromise between
stability and jitter. For more information, refer to DPLLnCTRLB.
Sigma-Delta DCO Filter Selection
The sigma-delta DAC low pass filter can be controlled and adjusted from the DCO filter selection register
DPLLnCTRLB.DCOFILTER[2:0]. For more information, refer to DPLLnCTRLB.
Related Links
14. GCLK - Generic Clock Controller
28.6.6 DMA Operation
Not applicable.
28.6.7 Interrupts
The OSCCTRL has the following interrupt sources:
• XOSCRDY - Multipurpose Crystal Oscillator Ready: A 0-to-1” transition on the STATUS.XOSCRDY
bit is detected
• CLKFAIL - Clock Failure . A “0-to-1” transition on the STATUS.CLKFAIL bit is detected.
• DFLLRDY - DFLL48m Ready: A “0-to-1” transition on the STATUS.DFLLRDY bit is detected
• DPLLnLOCKR - DPLLn Lock Rise: A “0-to-1” transition on the STATUS.DPLLnLOCKR bit is detected
• DPLLnLOCKF - DPLLn Lock Fall: A “0-to-1” transition on the STATUS.DPLLnLOCKF bit is detected
• DPLLnLTTO - DPLLn Lock Timer Time-out: A “0-to-1” transition on the STATUS.DPLLnLTTO bit is
detected
• DPLLnLDRTO - DPLLn Loop Divider Ratio Update Complete. A “0-to-1” transition on the
STATUS.DPLLnLDRTO bit is detected
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status
and Clear register (INTFLAG) is set when the interrupt condition occurs. Each interrupt can be
individually enabled by writing a one to the corresponding bit in the Interrupt Enable Set register
(INTENSET), and disabled by writing a one to the corresponding bit in the Interrupt Enable Clear register
(INTENCLR). An interrupt request is generated when the interrupt flag is set and the corresponding
interrupt is enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is
disabled or the OSCCTRL is reset. INTFLAG register for details on how to clear interrupt flags.
The OSCCTRL has one common interrupt request line for all the interrupt sources. The user must read
the INTFLAG register to determine which interrupt condition is present.
Note that interrupts must be globally enabled for interrupt requests to be generated.
28.6.8 Events
The CFD can generate the following output event:
• Clock Failure (CLKFAIL): Generated when the Clock Failure status bit is set in the Status register
(STATUS.CLKFAIL). The CFD event is not generated when the Clock Switch bit (STATUS.CLKSW)
in the Status register is set.
Writing a '1' to an Event Output bit in the Event Control register (EVCTRL.CFDEO) enables the CFD
output event. Writing a '0' to this bit disables the CFD output event. Refer to the Event System chapter for
details on configuring the event system.
SAM D5x/E5x Family Data Sheet
OSCCTRL – Oscillators Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 777